ONGC MODEL PAPER FOR PROGRAMMING/ ONGC Gt-2012 Model Paper- Programming

     ONGC  has been announced the written test for the various posts of the graduate trainee. In out of which post  graduate trainee for the programming discipline also recruited from the test.  The model papers for the programming candidates are given below…. 
        ONGC PAPER REVIEW held on 4 Nov 2012

Here some subject questions are given rest of the question will be in model paper-2.

                   

            MODEL PAPER FOR THE PROGRAMMING

1. Translator for low level programming language were termed as

          (A) Assembler    (B) Compiler

          (C) Linker          (D) Loader

   ANSWER: (A)

2. Analysis which determines the meaning of a statement once its    grammatical structure becomes known is termed as

         (A) Semantic analysis              (B) Syntax analysis

         (C) Regular analysis                 (D) General analysis

    ANSWER: (A)

3. Load address for the first word of the program is called

      (A) Linker address origin          (B) load address origin

(C) Phase library                         (D) absolute library

    ANSWER (B)

4. Symbolic names can be associated with

            (A) Information                         (B) data or instruction

            (C) operand                                (D) mnemonic operation

ANSWER: (B)

5. The translator which perform macro expansion is called a

          (A) Macro processor                 (B) Macro pre-processor

          (C) Micro pre-processor           (D) assembler

ANSWER- (B)

6. The decimal number 127 may be represented by

      (a) 1111 1111B

      (b) 1000 0000B

      (c) EEH, (d) 0111 1111

7. A byte corresponds to    (a) 4 bits      (b) 8 bits     (c) 16 bits      (d) 32 bits

8. The storage required for an image such as an X-ray is approximately

        (a) a few bytes

       (b) a few hundred bytes

       (c) a few gigabytes

       (d) in the megabyte range.

9. A gigabyte represents

       (a) 1 billion bytes

       (b) 1000 kilobytes

        (c) 230 bytes

       (d) 1024 bytes

ANSWER – a

10. A megabyte represents

     (a) 1 million bytes

     (b) 1000 kilobytes

     (c) 220 bytes  

     (d) 1024bytes

ANSWER- b

11. A Kb corresponds to

     (a) 1024 bits                                 (b) 1000 bytes

     (c) 2^10 bytes                                 (d) 2^10 bits

ANSWER-

12. A superscalar processor has

     (a) multiple functional units

      (b) a high clock speed

      (c) alarge amount of RAM

      (d) many I/O ports

ANSWER-

13. A 32-bit processor has

     (a) 32 registers                                (b) 32 I/O devices

     (c) 32 Mb of RAM                          (d) a 32-bit bus or 32-bit registers

ANSWER- d

14. Information is stored and transmitted inside a computer in

               (a) binary form                                    (b) ASCII code form

                (c) decimal form                                (d) alphanumeric form

ANSWER- a

15. The minimum number of bits required to store the hexadecimal number FF is

          (a) 2,             (b)4,                     (c) 8,                   (d) 16

ANSWER- b

16. A parity bit is

         (a) used to indicate uppercase letters      

          (b) used to detect errors

          (c) is the first bit in a byte

          (d) is the last bit in a byte

ANSWER- b

17. !A 20-bit address bus allows access to a memory of capacity

          (a) 1 Mb            (b) 2 Mb (c)          32Mb                   (d) 64 Mb

ANSWER- a

18. A 32-bit address bus allows access to a memory of capacity

      (a) 64 Mb           (b) 16 Mb             (c) 1Gb            (d) 4 Gb

ANSWER- a

19.!Clock speed is measured in

       (a) bits per second    (b) baud           (c) bytes           (d) Hertz

ANSWER-

20. On-chip cache has

    (a) lower access time than RAM           

    (b) larger capacity than off chip cache

     (c) its own data bus

    (d) become obsolete

ANSWER-

21. An FPU

      (a) makes integer arithmetic faster

      (b) makes pipelining more efficient

     (c) increases RAM capacity

     (d) makes some arithmetic calculations faster

ANSWER-

22. Pipelining improves CPU performance due to

        (a) reduced memory access time

        (b) increased clock speed

         (c) the introduction of parallelism

        (d) additional functional units

ANSWER- C

23. The system bus is made up of

            (a) data bus

            (b) data bus and address bus

            (c) data bus and control bus

           (d) data bus, control bus and address bus

ANSWER – d

24. The von Neumann bottleneck is due to

           (a) mismatch in speed between secondary and primary storage

           (b) mismatch in speed between the CPU and primary storage

            (c) slow speed of I/O devices

          (d) low clock speeds

ANSWER-

25. Cache memory enhances

           (a) memory capacity

           (b) memory access time

           (c) secondary storage capacity

           (d) secondary storage access time

ANSWER- B

26. Cache memory

       (a) has greater capacity than RAM

       (b) is faster to access than CPU registers

       (c) is permanent storage

       (d) faster to access than DRAM

ANSWER- D

  

The remaining subjects questions will be updates in the next paper paper please keep in touch next paper will be updated soon.

If you have any query in any question free to comment and make it better as possible.

MODEL PAPER-2 will be updated soon